1. Field of the Invention
The present invention relates to a frame transfer method and apparatus, and in particular to a method and apparatus for entering data into a content addressable memory (CAM) used for transferring or relaying an IP frame (hereinafter, simply referred to as frame) in a router or the like.
2. Description of the Related Art
FIG. 10 shows an arrangement of a prior art frame transfer apparatus using a content addressable memory. This frame transfer apparatus is composed of devices 1 and 2 sequentially and serially connected with a line bus B1 from a line interface LI, a bus bridge 3 further connected to the devices 1 and 2 with the line bus B1, a content addressable memory 4 connected to the bus bridge 3 with a local bus B2 and a CPU 5 further connected to the bus bridge 3 through a PCI bus B3. The PCI bus B3 is also connected to the devices 1 and 2.
The device 1 is an LSI, for example, having a function of processing data belonging to the first layer (PHY: physical layer) of the OSI reference model, or specifically processing data associated with a cable material, a connector shape and a mutual conversion system (regulation of voltage and the like) between data and electric signals.
Also, the device 2 is an LSI, for example, belonging to a MAC (Media Access Control) layer that is a lower layer within a data link layer in the OSI reference model, and having a function of processing data associated with a transmitting/receiving direction of a frame, a frame format, an error detecting method, and the like.
Also, the bus bridge 3 is an LSC (Load Sharing Controller) having a load balancing function of a frame (packet), determines a distributing destination (transferring destination) based on the header information of an arrived frame, rewrites source/destination MAC addresses, and transmits the frame to the destination of distribution.
It is also required that relay information necessary for the frame distribution is entered into the content addressable memory 4.
FIG. 11 shows a table format within the content addressable memory 4. In FIG. 11, an entry code (4 bits) is for identifying entry types (IPv4DA, IPv4SA, IPv6DA and IPv6SA). Also, a VID is a code for identifying a VLAN ID of an IP frame. An IP DA indicates a destination IP address of the IP frame, and an IP SA indicates a source IP address thereof.
Header information of the IP frame that is an object of the distribution is stored in the content addressable memory 4, so that as a result of a retrieval from the content addressable memory 4, the MAC address is rewritten for a hit frame to perform a packet transfer (normal operation corresponding to processing excluding step S5 in the example of a normal operation shown in FIG. 4 which will be described later).
In such a frame transfer apparatus, when the header information of the IP frame is entered into the content addressable memory 4, a data transfer between the PCI bus B3 where the CPU 5 is connected and the local bus B2 where the content addressable memory 4 is connected is performed through the bus bridge 3. Namely, when the CPU 5 accesses the content addressable memory 4 on the local bus B2, the CPU 5 firstly makes a request to the bus bridge 3 on the PCI bus B3 (FIG. 10(b)), so that a read cycle is generated for the content addressable memory 4 on the local bus B2, and after the header information is obtained, the header information is transferred through the PCI bus B3.
A timing chart for such an entry operation into the content addressable memory 4 is shown in FIG. 12A.
In FIG. 12A, “CLK 33” indicates a clock of the PCI bus (33 MHz). “AD[31:0]” indicates an address (ADR) and a data bus (WDT) of the PCI bus B3. “nCBE[3:0]” indicates an address command (CMD) and byte enable (BE) of the PCI bus B3. “PAR” indicates a parity (AP: address parity, DP: data parity) of the PCI bus. “nFRAME” indicates a frame signal of the PCI bus B3. “nIRDY” indicates an initiator ready signal of the PCI bus B3. “nDEVSEL” indicates a device selection signal of the PCI bus B3. “nTRDY” indicates a target ready signal of the PCI bus B3. “nSTOP” indicates a STOP signal of the PCI bus B3. “CLK2X” indicates a clock (156.25 MHz) of the local bus B2. “REQSTB” indicates a bus request signal of the local bus B2. “INST” indicates a bus command (Instruction) signal of the local bus B2. “GMASK” indicates a bus command (GlocalMask register selection) signal of the local bus B2. “REQDATA[71:0]” indicates a data bus of the local bus B2.
On the other hand, there is a packet processing system where packets transmitted from LAN housing parts are stored in the reception parts of the respective IAN housing parts without being stored in a CAM controller, so that in the middle of storing the data of the packets, the destination address and source address of the packet data are extracted by the CAM controller, and filtering and routing are executed (see e.g. patent document 1).
Also, there is a device and method for transferring data in which a bus bridge is connected between a system bus and a local bus, data transferred on the system bus among a CPU, I/O equipment and a main storage device are held via an associated memory control part into an associated memory, and when access from the I/O equipment on the local bus to the data occurs, the data are transferred from the associated memory to the. I/O equipment (see e.g. patent document 2).    [Patent document 1] Japanese Patent Application Laid-open No. 8-70319    [Patent document 2] Japanese Patent Application Laid-open No. 2002-24162
In the prior art frame transfer apparatus shown in FIG. 10, the data transfer is slowed when the PCI bus B3 is in use since a delay time occurs before the bus bridge 3 on the PCI bus B3 is accessed and the data is transferred to the content addressable memory 4 from the bus bridge 3. Also, if the data volume entered into the content addressable memory 4 is large, there has been a problem that an enormous amount of time is required before the completion of the entire data entry since the data conversion between the PCI bus B3 and the local bus B2 takes time.